The miniaturization of ICs is sustained by the scaling theory of physics, which states that a transistor device operates reliably at a higher speed when the device size and voltage supply (Vdd) are scaled down by the same factor. At 130 nanometers and below, or at Vdd of 1.2 volts and below, the supply integrity of power and ground networks is emerging as a major limitation for high-performance system-on-chip designs. The power integrity (PI) issue, which arises from increasing current density and larger dynamic current spikes, can only be addressed effectively from the perspectives of both design and verification.


Apache Design Automation introduces RedHawk-SDL (Static, Dynamic, and L inductance) it is the industry’s first dynamic cell-based power-ground design and verification solution with integrated transistor-level characterization for assured accuracy. RedHawk-SDL analyzes the effects of on-chip and off-chip (package) inductance, simultaneous switching (core, memory, and I/O), decoupling capacitance (intrinsic and intentional), and dynamic voltage drop impact on timing on big SoCs.

Axis Systems

Axis' mission is to dramatically increase the verification productivity of system and SoC designers around the world by closing the verification gap--the current discontinuity between the development of increasingly complex chips and the ability to verify their accuracy. On a single system, and with one design database, our patented ReConfiguarable Computing (RCC) technology provides software simulation, accelerated simulation, system emulation, and hardware/software co-verification for large, complex electronic system and system-on-a-chip designs.


XoC™ is an all-inclusive, unified verification system for ARM microprocessor-based designs that reduces communications overhead and eliminates time-intensive integration efforts for design teams. XoC enables the smooth transition between all nine different operating modes from block-level testing through application software and features a Co-Verification Debugger that creates a common communication environment between hardware and software teams through AMBA™ transactions.


Xtreme® offers simulation, acceleration, emulation, and hardware/software co-verification, in a unified, compact, server-sized system, at speeds of up to 1 million cycles per second on designs of up to 100 million ASIC gates. Xtreme provides full debugging capabilities throughout the entire verification flow, allowing emulation to start much earlier in the design cycle.


Xcite® offers simulation acceleration performance of up to 100,000 cycles per second on designs of up to 10 million ASIC gates. Xcite delivers hardware performance with software debugging capabilities. Designers can run simulation as fast as possible while quickly detecting and isolating design problems.

Solidify - Static Functional Verification for HDL Designers

The increasing complexity of system-on-a-chip and ASIC designs has caused an ever-widening gap between what can be designed and what can be. It is estimated that between 50-70% of the time required to design a complex IC is spent in verifying that the functionality of the system is correct. Bugs in a design are least expensive to fix just after they are created.

At this stage the design is still fresh in the designer's mind and other parts of the project or other design team members are unaffected. Bugs are at least an order of magnitude more expensive to fix during system integration. In this phase it takes more time and people to analyze the cause, regression tests must be rerun, and the entire group may be delayed. These challenges are giving rise to some exciting new tools and approaches in Verification techniques, one such verification technique is Static Functional Verification.

Solidify is the leading static functional verification tool for RTL level Verilog and VHDL designs. Solidify, based on proprietary breakthrough technology, is able to exhaustively verify functional behavior as the HDL code is developed. Solidify’s static approach uses no vectors, eliminating the time and effort needed to write, run and modify test vectors and test benches.

Solidify™, is an interactive, easy-to-use design tool for static functional verification. RTL designers, architects, and validation engineers building complex ICs and IP blocks will improve design quality, shorten design cycles, and eliminate unnecessary simulation with Solidify. Besides RTL verification, Solidify detects inconsistencies coming from functional specifications, and includes code coverage technology for verification assurance. In one tool, Solidify, offers designers a better alternative to test vector generation, functional simulation, and code coverage by using a static approach without vectors.


NSpice - Next-Generation SPICE for chips, multi-gigabit systems


NSPICE is the industry's first HSPICE compatible simulator that performs mixed-domain simulation between chips and systems using actual S-parameter data, without translation or fitting. The product provides a seamless and accurate simulation path - from chip to package to board to backplane and back to chip - using direct S-parameters, thereby eliminating the inaccuracies of lumped RLC model approximations.

NSPICE Highlights

° Mixed-domain simulation using direct S-parameters for multi-gigabit application

      • Fastest time to eye diagram
      • Accuracy proven by silicon measurement
      • Works across a broad frequency range up to 20+ GHz

° Dramatic performance, capacity and convergence improvements over HSPICE

      • Meets or beats HSPICE accuracy
      • Over 1 million elements can be simulated
      • Fully compatible with HSPICE netlists and commands

° Accurate transient analysis of PLLs and high-speed drivers with packages and boards

° Signal integrity and nanometer checks for device stress, headroom, leakage and IR drop